Memory cells such as, for example, flash memory cells may be used to store data. One type of flash memory cell is a split-gate flash memory cell, which may include a spacer (e.g. poly spacer) as a select gate (SG) in addition to a gate stack (e.g. double poly stack) including a floating gate (FG) and a control gate (CG) of the memory cell. For this type of memory cell, it may be desirable to improve or optimize the formation of source/drain junctions in order to achieve fast programming (abrupt junction) while avoiding short channel effects. For example, formation of lightly doped (LDD) junctions in the memory cell may reduce short channel effects.
Improving or optimizing source/drain junction formation may include using separate implants for the source/drain junctions. For separate source/drain junction implants, conventional methods may include adding two highly critical masks, which may have to be aligned to the gate patterning by either blocking the source side or the drain side of the cell.